Many digital systems use signal processing to remove unwanted noise, to provide spectral shaping, or to perform signal detection or analysis. Two types of filters that provide these functions are Finite Impulse Response (FIR) filters and infinite impulse response (IIR) filters. FIR filters are used in systems that require linear phase and have an inherently stable structure whereas IIR filters are used in systems that can tolerate phase distortion. Typical filter applications include signal preconditioning, band selection, and low pass filtering.
FIR filters have a linear phase and inherent stability that makes FIR filters sufficiently attractive to be designed into a large number of systems. Unfortunately, however, since FIR filters are of a higher order than are IIR filters, implementing a FIR filter is generally more computationally expensive. A conventional FIR filter is basically a weighted tapped delay line. The filter design process involves identifying coefficients that match the frequency response specified for the particular system for which the FIR filter is being designed. In this way, the coefficients determine the response of the filter. The signal frequencies that pass through the filter can be modified simply by changing the values of the coefficients or by adding more coefficients.
Digital signal processors (DSPs) have a limited number of multiplier accumulators (MACs) which require many clock cycles to compute each output values since the number of cycles is directly related to the order of the filter. Once a particular FIR filter design has been finalized, the FIR filter can take the form of a dedicated hardware solution which typically can achieve one output per clock cycle. However, by using a programmable integrated circuit, such as a programmable logic device (PLD) such as those manufactured by the Altera Corporation of San Jose Calif., a fully parallel, pipelined FIR filter implemented, or “fitted”, in a PLD and can operate at data rates above 100 million samples per second (MSPS), thereby making PLDs an ideal platform for high speed filtering applications.
Unfortunately however, conventional approaches to implementing a particular FIR filter in a PLD is time consuming and expensive. More specifically, a designer must first define an ideal frequency response for the desired filter. Based upon the ideal frequency response, the filter designer then must generate a set of desired FIR filter response data in the form of design architectural data blocks. Based upon the desired filter response, the behavioral characteristics of the FIR filter are then determined based upon floating-point values that are converted to fixed-point filter coefficients. Once the particular filter coefficients have been calculated, then an interim hardware filter architecture is determined. By hardware filter architecture it is meant whether the FIR filter is to be configured as a parallel or serial type FIR filter. In some applications, a serial type FIR filter configuration may be appropriate whereas in other applications a parallel type FIR filter configuration may be appropriate. A simulation must then be iteratively run on the interim hardware filter architecture to ascertain whether or not FIR filter, as currently configured, meets the original design specifications. Once an appropriate filter design has been established based upon an acceptable simulation run, the FIR filter design is synthesized and fitted to a target PLD by an appropriate placing and routing program.
Typical cycle times for the conventional FIR filter design cycle described above takes on the average, at least 6 weeks to complete. This long cycle time increases costs, slows introduction of new products, and delays release of system upgrades all of which negatively affect profitability and new product introductions.
Therefore, what is desired is an efficient method and apparatus for implementing a FIR filter in a programmable logic device.